;buildInfoPackage: chisel3, version: 3.4.1, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit EndianCnvt : 
  module EndianCnvt : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip NumIn : UInt<128>, NumOut : UInt<128>}
    
    wire temp : UInt<8>[16] @[sub_module.scala 32:32]
    wire _WIRE : UInt<128>
    _WIRE <= io.NumIn
    node _T = bits(_WIRE, 7, 0) @[sub_module.scala 32:32]
    temp[0] <= _T @[sub_module.scala 32:32]
    node _T_1 = bits(_WIRE, 15, 8) @[sub_module.scala 32:32]
    temp[1] <= _T_1 @[sub_module.scala 32:32]
    node _T_2 = bits(_WIRE, 23, 16) @[sub_module.scala 32:32]
    temp[2] <= _T_2 @[sub_module.scala 32:32]
    node _T_3 = bits(_WIRE, 31, 24) @[sub_module.scala 32:32]
    temp[3] <= _T_3 @[sub_module.scala 32:32]
    node _T_4 = bits(_WIRE, 39, 32) @[sub_module.scala 32:32]
    temp[4] <= _T_4 @[sub_module.scala 32:32]
    node _T_5 = bits(_WIRE, 47, 40) @[sub_module.scala 32:32]
    temp[5] <= _T_5 @[sub_module.scala 32:32]
    node _T_6 = bits(_WIRE, 55, 48) @[sub_module.scala 32:32]
    temp[6] <= _T_6 @[sub_module.scala 32:32]
    node _T_7 = bits(_WIRE, 63, 56) @[sub_module.scala 32:32]
    temp[7] <= _T_7 @[sub_module.scala 32:32]
    node _T_8 = bits(_WIRE, 71, 64) @[sub_module.scala 32:32]
    temp[8] <= _T_8 @[sub_module.scala 32:32]
    node _T_9 = bits(_WIRE, 79, 72) @[sub_module.scala 32:32]
    temp[9] <= _T_9 @[sub_module.scala 32:32]
    node _T_10 = bits(_WIRE, 87, 80) @[sub_module.scala 32:32]
    temp[10] <= _T_10 @[sub_module.scala 32:32]
    node _T_11 = bits(_WIRE, 95, 88) @[sub_module.scala 32:32]
    temp[11] <= _T_11 @[sub_module.scala 32:32]
    node _T_12 = bits(_WIRE, 103, 96) @[sub_module.scala 32:32]
    temp[12] <= _T_12 @[sub_module.scala 32:32]
    node _T_13 = bits(_WIRE, 111, 104) @[sub_module.scala 32:32]
    temp[13] <= _T_13 @[sub_module.scala 32:32]
    node _T_14 = bits(_WIRE, 119, 112) @[sub_module.scala 32:32]
    temp[14] <= _T_14 @[sub_module.scala 32:32]
    node _T_15 = bits(_WIRE, 127, 120) @[sub_module.scala 32:32]
    temp[15] <= _T_15 @[sub_module.scala 32:32]
    wire temp2 : UInt<8>[16] @[sub_module.scala 33:19]
    temp2[0] <= temp[15] @[sub_module.scala 34:9]
    temp2[1] <= temp[14] @[sub_module.scala 34:9]
    temp2[2] <= temp[13] @[sub_module.scala 34:9]
    temp2[3] <= temp[12] @[sub_module.scala 34:9]
    temp2[4] <= temp[11] @[sub_module.scala 34:9]
    temp2[5] <= temp[10] @[sub_module.scala 34:9]
    temp2[6] <= temp[9] @[sub_module.scala 34:9]
    temp2[7] <= temp[8] @[sub_module.scala 34:9]
    temp2[8] <= temp[7] @[sub_module.scala 34:9]
    temp2[9] <= temp[6] @[sub_module.scala 34:9]
    temp2[10] <= temp[5] @[sub_module.scala 34:9]
    temp2[11] <= temp[4] @[sub_module.scala 34:9]
    temp2[12] <= temp[3] @[sub_module.scala 34:9]
    temp2[13] <= temp[2] @[sub_module.scala 34:9]
    temp2[14] <= temp[1] @[sub_module.scala 34:9]
    temp2[15] <= temp[0] @[sub_module.scala 34:9]
    node lo_lo_lo = cat(temp2[1], temp2[0]) @[sub_module.scala 35:28]
    node lo_lo_hi = cat(temp2[3], temp2[2]) @[sub_module.scala 35:28]
    node lo_lo = cat(lo_lo_hi, lo_lo_lo) @[sub_module.scala 35:28]
    node lo_hi_lo = cat(temp2[5], temp2[4]) @[sub_module.scala 35:28]
    node lo_hi_hi = cat(temp2[7], temp2[6]) @[sub_module.scala 35:28]
    node lo_hi = cat(lo_hi_hi, lo_hi_lo) @[sub_module.scala 35:28]
    node lo = cat(lo_hi, lo_lo) @[sub_module.scala 35:28]
    node hi_lo_lo = cat(temp2[9], temp2[8]) @[sub_module.scala 35:28]
    node hi_lo_hi = cat(temp2[11], temp2[10]) @[sub_module.scala 35:28]
    node hi_lo = cat(hi_lo_hi, hi_lo_lo) @[sub_module.scala 35:28]
    node hi_hi_lo = cat(temp2[13], temp2[12]) @[sub_module.scala 35:28]
    node hi_hi_hi = cat(temp2[15], temp2[14]) @[sub_module.scala 35:28]
    node hi_hi = cat(hi_hi_hi, hi_hi_lo) @[sub_module.scala 35:28]
    node hi = cat(hi_hi, hi_lo) @[sub_module.scala 35:28]
    node _T_16 = cat(hi, lo) @[sub_module.scala 35:28]
    io.NumOut <= _T_16 @[sub_module.scala 35:13]
    
